Impact of the gate oxide reliability of SiC MOSFETs on the junction temperature estimation using temperature sensitive electrical parameters

Bias temperature instability (BTI) is more problematic in SiC power MOSFETs due to the occurrence of higher interface state traps and fixed oxide traps compared to traditional silicon MOS interfaces where there are no carbon atoms degrading the atomically smooth Si/SiO2 interface. The use of temperature sensitive electrical parameters (TSEPs) for measuring the junction temperature and enabling health monitoring based on junction temperature identification is a promising technique for increasing the reliability of power devices, however in the light of increased BTI in SiC devices, this must be carefully assessed. This paper evaluates how BTI of SiC power MOSFETs under high temperature gate bias stresses affects the electrical parameters used as TSEPs and its impact on condition monitoring

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiOx/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications

Crosstalk in SiC power MOSFETs for evaluation of threshold voltage shift caused by bias temperature instability

Threshold voltage drift from Bias Temperature Instability is known to be a reliability concern for SiC MOSFETs. Negative bias temperature instability (NBTI) results from positive charge trapping at the gate dielectric interface and is more problematic in SiC due to the higher interface trap density. Turning SiC MOSFETs OFF with negative voltages to avoid Miller coupling induced cross-talk can cause VTH shifts in periods with long standby duration and high temperatures. This paper proposes a novel test method for BTI characterization that relies on measuring the shoot-through current and charge during switching transients. The method exploits the Miller coupling between 2 devices in the same phase and uses the shoot-through current from parasitic turn-ON to monitor VTH. Standard techniques require the use of static measurements (typically from a parameter analyzer or a curve tracer) to determine the threshold voltage shift. These conventional methods can underestimate the VTH shift since the recovery from charge de-trapping can mask the true extent of the problem. The proposed methodology uses the actual converter environment to investigate the VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, it avoids the problem of VTH recovery and is therefore more accurate in VTH shift characterization

A novel non-intrusive technique for BTI characterization in SiC MOSFETs

Threshold voltage ( $V_{TH}$ ) shift due to Bias Temperature Instability (BTI) is a well-known problem in SiC-MOSFETs that occurs due to oxide traps in the $SiC/SiO_2$ gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC-MOSFETs makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which $V_{TH}$ shift is monitored. However, some recovery occurs between the end of the stress and $V_{TH}$ characterisation, thereby potentially under-estimating the extent of the problem. In applications where the SiC-MOSFET is turned OFF with a negative bias at high temperature, if $V_{TH}$ shift is severe enough there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn-ON. In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring $V_{TH}$ shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar SiC-MOSFETs due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess $V_{TH}$ shift dynamically during BTI characterization tests

Impact of BTI induced threshold voltage shifts in shoot-through currents from crosstalk in SiC MOSFETs

In this paper a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-ON to characterize the impact of Bias Temperature Instability (BTI) induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge de-trapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal and polarity of the stress have been studied for a set of commercially available SiC MOSFETs

Characterizing threshold voltage shifts and recovery in Schottky gate and Ohmic gate GaN HEMTs

Threshold voltage shift in normally-OFF GaN High Electron Mobility Transistors (HEMTs) is an important reliability concern in GaN devices. Differences in device architecture between Schottky gate and Ohmic gate normally-OFF GaN HEMTs means that there are important differences in the physical mechanism behind threshold voltage shift due to gate stress. In this paper, a non-intrusive technique for the characterization of threshold voltage shift is applied to both technologies. The technique relies on using a sensing current to measure the third quadrant voltage before and after gate-voltage stress. The results show that in Schottky Gate GaN HEMTs, a positive threshold voltage shift occurs at low gate stress voltages due to electron trapping in the GaN/AlGaN interface while at higher gate stress voltages, the threshold voltage shift becomes negative due to hole trapping and accumulation. The stress time has a fundamental role on the measured threshold voltage shift at medium gate voltage levels and pulsed gate stresses are able to capture this phenomenon. For the Ohmic Gate GaN HEMTs, only a negative threshold voltage shift is observed for all stress currents with no apparent shift as the junction temperature is increased

Trade-offs between gate oxide protection and performance in SiC MOSFETs

The reliability of gate oxides in SiC MOSFETs has come under increased scrutiny due to reduced performance under time dependent dielectric breakdown and increased threshold voltage instability. This paper investigates how 10% gate voltage (V GS ) derating in SiC MOSFETs can be implemented with minimal impact on loss performance. Using experimental measurements and electrothermal simulations of power converters, the trade-off between reduced V GS and conversion loss is investigated. It is shown that 10% V GS de-rating increases the ON-state resistance by 10% and the turn-ON switching energy by 7% average while the turn-OFF switching energy is unaffected. The low temperature sensitivity of the ON-state losses in SiC MOSFETs can be exploited since the rise in junction temperature due to V GS derating is marginal, unlike Si devices where ON-state resistance rises significantly with temperature. The load current and switching frequency influences the effectiveness of V GS derating. It is also shown that reducing the gate drive output impedance can compensate for V GS derating at high switching frequencies, with reduced total loss penalization. This may be important for protecting the gate oxide and enhancing its reliability

Non-intrusive methodologies for characterization of bias temperature instability in SiC power MOSFETs

The gate oxide reliability of SiC power MOSFETs remains a challenge, despite the improvements of the new generation power devices. The threshold voltage drift caused by Bias Temperature Instability (BTI) has been subject of different studies and methods have been proposed to evaluate the real magnitude of the threshold voltage shift. These methodologies usually focus on the characterization of the threshold voltage shift, rather than its implications to the operation or how the threshold voltage shift can be detected during the application. This paper presents two non-intrusive methodologies which can assess and determine the impact of BTI-induced. The proposed methodologies are able to capture the peak shift and subsequent recovery after stress removal

The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes